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innovative power tm - 1 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. rev 2, 16-nov-09 six channel integrated power management ic for handheld portable equipment act8796 pb-free system blo ck diagram features ? multiple patents pending ? six integrated regulators ? 750ma pwm step-down dc/dc ? 750ma pwm step-down dc/dc ? 550ma pwm step-down dc/dc ? 250ma low noise ldo ? 250ma low noise ldo ? 250ma low noise ldo ? i 2 c tm compatible serial interface ? programmable output voltages ? configurable operating modes ? minimal external components ? 4x4mm, thin-qfn (tqfn44-24) package ? only 0.75mm height ? rohs compliant applications ? portable devices and pdas ? wireless handhelds ? dmb enabled devices ? gps receivers, etc. general description the patent-pending act8796 is a complete, cost- effective, highly-efficient activepmu tm power management solution that is ideal for a wide range of portable handheld equipment. this device integrates three step-down dc/dc converters and three low dropout linear regulators (ldos) into a single, thin, space-saving package. an i 2 c serial interface provides prog rammability for the dc/dc converters and ldos. reg1, reg2 and reg3 are fixed-frequency, current-mode pwm step-down dc/dc converters that are optimized for high efficiency and are capable of supplying up to 750ma, 750ma and 550ma, respectively. reg4, reg5 and reg6 are low noise, high psrr linear regulators that are capable of supplying up to 250ma each. the act8796 is available in a tiny 4mm4mm 24- pin thin-qfn package that is just 0.75mm thin. act8796 system control reg2 step-down dc/dc reg1 step-down dc/dc reg3 step-down dc/dc reg4 ldo reg5 ldo reg6 ldo on3 scl sda battery nmstr pwrhld out4 0.645v to 3.7v up to 250ma out2 1.1v to 4.4v up to 750ma out6 1.4v to 3.7v up to 250ma out3 1.1v to 4.4v up to 550ma out1 1.1v to 4.4v up to 750ma out5 1.4v to 3.7v up to 250ma nrsto a ctive-semi pmu pmu pmu tm a ctive
act8796 rev 2, 16-nov-09 innovative power tm - 2 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi functional block diagram reg1 reg2 vp1 vp2 gp12 gp12 sw2 sw1 nmstr push button inl out2 out1 out2 out1 on3 ldo reg4 ldo reg5 ldo reg6 out4 out5 out6 inl reg3 vp3 gp3 sw3 out3 out3 system control ga act8796 out6 out5 out4 to battery pwrhld to battery to battery to battery refbp reference sda scl serial interface nrsto out2
act8796 rev 2, 16-nov-09 innovative power tm - 3 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi pin configuration ordering information cd top view thin - qfn (tqfn44-24) out3 ga refbp pwrhld on3 sda ga nmstr out4 vp2 sw2 gp12 sw1 vp1 vp3 sw3 gp3 out5 out6 inl 1 2 3 4 5 6 18 17 16 15 14 13 19 20 21 22 23 24 12 11 10 9 8 7 out2 out1 scl act8796 ep nrsto part number v out1 v out2 package pins temperature range act8796qlghw-t 3.0v 3.3v tq fn44-24 24 -40c to +85c v out3 1.35v v out4 1.35v v out5 2.8v v out6 1.8v c : output voltage options detailed in this table represent st andard voltage options, and are available for samples or production orders. additional output voltage options, as detailed in the output voltage codes table, are available for pro duction subject to minimum order quantities. contact active-semi for more informatio n regarding semi-custom output voltage combinations. d : all active-semi components are rohs compliant and with pb-free plating unless specified differently. the term pb-free means semiconductor products that are in compliance with current rohs (restriction of haza rdous substances) standards. output voltage codes (v out1 and v out2 ) c d e f g h 1.2v 1.5v 1.8v 2.5v 3.0v 3.3v i 2.8v
act8796 rev 2, 16-nov-09 innovative power tm - 4 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi pin descriptions pin name description 1 out4 output voltage for reg4. capable of delivering up to 250ma of output current. the output is dis- charged to g with 650 ? load when disabled. 2 scl clock input for i 2 c serial interface. data is read on the rising edge of the clock. 3 sda data input for i 2 c serial interface. data is read on the rising edge of the clock. 4, 17 ga analog ground. connect ga directly to a quiet ground node. connect ga, gp12, and gp3 together at a single point as close to the ic as possible. 5 nmstr master enable input. drive nmstr to ga or to a logic low to enable the ic. reg1, reg2, and reg3 are enabled while nmstr is asserted. 6 nrsto open-drain reset output. nrsto asserts low for the reset timeout period of 300ms whenever the ic is enabled. 7 out1 output feedback sense for reg1. connect this pin directly to the output node to connect the inter- nal feedback network to the output voltage. 8 vp1 power input for reg1. bypass to gp12 with a high quality ceramic capacitor placed as close as possible to the ic. 9 sw1 switching node output for reg1. connect th is pin to the switching end of the inductor. 10 gp12 power ground for reg1 and reg2. connect ga, gp12, and gp3 together at a single point as close to the ic as possible. 11 sw2 switching node output for reg2. connect th is pin to the switching end of the inductor. 12 vp2 power input for reg2. bypass to gp12 with a high quality ceramic capacitor placed as close as possible to the ic. 13 out2 output feedback sense for reg2. connect this pin directly to the output node to connect the inter- nal feedback network to the output voltage. 14 on3 enable input for reg3, on3 is functional only when pwrhld is driven high. drive on3 to a logic high to turn on the reg3. drive on3 to a logic low to turn off the reg3. 15 pwrhld power hold input. drive pwrhld to logic high to enable the ic. drive pwrhld to a logic low to disable all regulators. 16 refbp reference noise bypass. connect a 0.01f ceramic capacitor from refbp to ga. this pin is dis- charged to ga in shutdown. 18 out3 output feedback sense for reg3. connect this pin directly to the output node to connect the inter- nal feedback network to the output voltage. 19 vp3 power input for reg3. bypass to gp3 with a high quality ceramic capacitor placed as close as possible to the ic. 20 sw3 switching node output for reg3. connect th is pin to the switching end of the inductor. 21 gp3 power ground for reg3. connect ga, gp12, and gp3 t ogether at a single point as close to the ic as possible. 22 out5 output voltage for reg5. capable of delivering up to 250ma of output current. the output is dis- charged to g with 650 ? load when disabled. 23 out6 output voltage for reg6. capable of delivering up to 250ma of output current. the output is dis- charged to g with 650 ? load when disabled. 24 inl power input for reg4, reg5 and reg6. bypass to ga with a high quality ceramic capacitor placed as close as possible to the ic. ep ep exposed pad. must be soldered to ground on pcb.
act8796 rev 2, 16-nov-09 innovative power tm - 5 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi absolute maximum ratings c parameter value unit vp1, vp2, sw1, sw2 to gp12 vp3, sw3 to gp3 scl, sda, inl, out1, out2, out3, out4, out5, out6, on3, refbp, nrsto, pwrhld, nmstr to ga -0.3 to +6 v sw1 to vp1 sw2 to vp2 sw3 to vp3 -6 to +0.3 v gp12, gp3 to ga -0.3 to +0.3 v junction to ambient thermal resistance ( ja ) 30 c/w operating temperature range -40 to 85 c junction temperature 125 c storage temperature -55 to 150 c lead temperature (soldering, 10 sec) 300 c rms power dissipation (t a = 70c) 1.8 w c : do not exceed these limits to prevent damage to the device. exposure to absolute maximum rati ng conditions for long periods m ay affect device reliability.
system management act8796 rev 2, 16-nov-09 innovative power tm - 6 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi key: r: read-only bits. no default assigned. v: default values depend on voltage option. default values may vary. note: addresses other than those specified in table 1 may be used for factory settings. do not access any registers other than those specified in table 1. register descriptions table 1: global register map output address data (default value) hex a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 reg1 10h 0 0 0 1 0 0 0 0 r v v v v v v v reg1 11h 0 0 0 1 0 0 0 1 r r r r r r r 0 reg1 12h 0 0 0 1 0 0 1 0 r r r r r r r r reg1 13h 0 0 0 1 0 0 1 1 r r r r r 0 r 1 reg2 20h 0 0 1 0 0 0 0 0 r v v v v v v v reg2 21h 0 0 1 0 0 0 0 1 r r r r r r r 0 reg2 22h 0 0 1 0 0 0 1 0 r r r r r r r r reg2 23h 0 0 1 0 0 0 1 1 r r r r r 0 r 1 reg3 30h 0 0 1 1 0 0 0 0 r v v v v v v v reg3 31h 0 0 1 1 0 0 0 1 r r r r r r r 0 reg3 32h 0 0 1 1 0 0 1 0 r r r r r r r r reg3 33h 0 0 1 1 0 0 1 1 r r r r r 0 r 1 reg4 03h 0 0 0 0 0 0 1 1 r v v v v v v v reg4 40h 0 1 0 0 0 0 0 0 r r 0 r r r r r reg5 41h 0 1 0 0 0 0 0 1 r r 0 v v v v v reg6 42h 0 1 0 0 0 0 1 0 r r 0 v v v v v reg456cfg 43h 0 1 0 0 0 0 1 1 r r r 1 1 1 0 r
system management act8796 rev 2, 16-nov-09 innovative power tm - 7 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi typical performanc e characteristics (v vsys = 3.6v, t a = 25c, unless otherwise specified.) oscillator frequency vs. temperature frequency (mhz) temperature (c) 1.71 1.50 act8796-001 1.68 1.65 1.62 1.59 1.56 1.53 85 -20 -40 0 20 40 60 startup sequence act8796-002 ch1 ch2 ch3 ch1: v nmstr , 5v/div ch2: v nrsto , 2v/div ch3: v pwrhld , 5v/div ch4: v out1 , 2v/div ch4 time: 100ms/div
system management act8796 rev 2, 16-nov-09 innovative power tm - 8 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi electrical characteristics (v inl = 3.6v, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit inl operating voltage range 2.6 5.5 v inl uvlo threshold inl voltage rising 2.25 2.4 2.55 v inl uvlo hysteresis inl voltage falling 80 mv oscillator frequency 1.35 1.6 1.85 mhz inl supply current pwrhld = on3 = ga 1.5 a nmstr internal pull-up resistance 250 500 k ? logic high input voltage pwrhld, on3, nmstr 1.4 v logic low input voltage pwrhld, on3, nmstr 0.4 v logic low output voltage i sink = 5ma 0.3 v thermal shutdown temperature temperature rising 160 c thermal shutdown hysteresis temperature falling 20 c leakage current nrsto, v nrsto = 4.2v 1 a nrsto delay 240 300 360 ms
system management act8796 rev 2, 16-nov-09 innovative power tm - 9 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi i 2 c interface electrical characteristics (v inl = 3.6v, t a = 25c, unless otherwise specified.) figure 1: i 2 c serial bus timing parameter test conditions min typ max unit scl, sda low input voltage 0.4 v scl, sda high input voltage 1.4 v scl, sda leakage current 1 a sda low output voltage i ol = 5ma 0.3 v scl clock period, t scl f scl clock freq = 400khz 2.5 s sda data in setup time to scl high, t su 100 ns sda data out hold time after scl low, t hd 300 ns sda data low setup time to scl low, t st start condition 100 ns sda data high hold time after clock high, t hp stop condition 100 ns
system management act8796 rev 2, 16-nov-09 innovative power tm - 10 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi general description the act8796 offers an array of system management functions that allow it to provide optimal performance in a wide range of applications. i 2 c serial interface at the core of the act8796's flexible architecture is an i 2 c interface that permits optional programming capability to enhance overall system performance. to ensure compatibility with a wide range of system processors, the act8796 uses standard i 2 c commands; i 2 c write-byte commands are used to program the act8796, and i 2 c read-byte commands are used to read the act8796's internal registers. the act8796 always operates as a slave device, and is addressed using a 7-bit slave address followed by an eighth bit, which indicates whether the transaction is a read-operation or a write-operation, [1011011x]. sda is a bi-directional data line and scl is a clock input. the master initiates a transaction by issuing a start condition, defined by sda transitioning from high to low while scl is high. data is transferred in 8-bit packets, beginning with the msb, and is clocked-in on the rising edge of scl. each packet of data is followed by an acknowledge (ack) bit, used to confirm that the data was transmitted successfully. for more information regarding the i 2 c 2-wire serial interface, go to the nxp website: http://www.nxp.com system startup and shutdown the act8796 features a flexible control architecture that supports a variety of software- controlled enable/disable functions that make it a simple yet flexible and highly configurable solution. the act8796 is automatically enabled when either of the following conditions exists: 1) nmstr is asserted low, or 2) pwrhld is asserted high. if either of these conditions is true, the act8796 enables reg1, reg2, reg4, and may be reg3 powering up the system processor so that the startup and shutdown sequences may be controlled via software. these startup conditions are described in detail below. manual enable due to asserting nmstr low system startup is initiated when the user presses the push-button, asserting nmstr low. when this occurs, reg1, reg2, reg3, and reg4 are enabled and nrsto is asserted low to hold the microprocessor in reset for 260ms. nrsto goes high-z upon expiration of the reset timer, de- asserting the processor's reset input and allowing the microprocessor to initiate its power up sequence. once the power-up routine is successfully completed, the microprocessor must assert pwrhld so that the act8796 remains enabled after the push-button is released by the user. upon completion of the start-up sequence the processor assumes control of the power system and all further operation is software-controlled. manual enable due to asserting pwrhld high the act8796 is compatible with applications that do not utilize its push-button control function, and may be enabled by simply driving pwrhld to a logic-high to enable reg1, reg2, and reg4. in this case, the signal driving pwrhld controls enable/disable timing, although software-controlled enable/disable sequences are still supported if the processor assumes control of the power system once the startup sequence is completed. shutdown sequence once a successful power-up routine is completed, the system processor cont rols the operation of the power system, including the system shutdown timing and sequence. when using the application circuits shown in figure 2, the nirq signal is asserted when nmstr is asserted low, providing a simple means of alerting the system processor when the user wishes to shut the system down. asserting nirq interrupts the system processor, initiating an interrupt service routine in the processor which will reveal that the user pressed the push-button. the microprocessor may validate the input, such as by ensuring that the push-button is asserted for a minimum amount of time, then initiates a software contro lled power-down routine, the final step of which is to de-assert the pwrhld input, disabling the regulators and shutting the system down. functional description
system management act8796 rev 2, 16-nov-09 innovative power tm - 11 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi nmstr enable input in most applications, connect nmstr to an active low, momentary push-butt on switch to utilize the act8796's closed-loop enable/disable functionality. if a momentary-on switch is not used, drive nmstr to ga or to a logic low to initiate a startup sequence. enable/disable inputs the act8796 provides two manual enable/disable inputs, pwrhld and on3. pwrhld is the master enable input. when driven high, pwrhld enables reg1, reg2, and reg4, and also activates the enable/disable control logic for the other regulators. on3 is the enable input for reg3, and is active when either of the following conditions exists: 1) nmstr is asserted low, or 2) pwrhld is asserted high. power-on reset output the act8796 integrates a 260ms power-on reset generator, reducing system size and cost. nrsto is an open-drain output. connect a 10k ? or greater pull-up resistor from nrsto to an appropriate voltage supply. nrsto asserts low upon startup and remains low until the reset-timeout period expires, at which point nrsto goes high-z. nirq output figure 2 shows two simple circuits that can be used to generate nirq, a processor interrupt signal, which can be used as part of the act8796?s push- button control logic. this signal is typically used to drive the interrupt input of the system processor, and is useful in a variety of software-controlled enable/disable control routines. figure 2a provides an active-low, open-collector push-button status output that sinks current when nmstr is driven to a logic-low. figure 2b provides an active-high, open- collector push-button status output that sources current when nmstr is driven to a logic-low. thermal shutdown the act8796 integrates thermal shutdown protection circuitry to prevent damage resulting from excessive thermal stress, as may be encountered under fault conditions. this circuitry disables all regulators if the act8796 die temperature exceeds 160c, and prevents the regulators from being enabled until the ic temperature drops by 20c (typ). functional description (cont?d) act8796 pb pb nmstr act8796 100k 100k nirq out2 v cc cpu 500k out2 v cc nirq 100k 100k inl (a) (b) figure 2: simple circuits
step-down dc/dc converters act8796 rev 2, 16-nov-09 innovative power tm - 12 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi c : v nom1 refers to the nominal output voltage level for v out1 as defined by the ordering information section. electrical characteristics (reg1) (v vp1 = 3.6v, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit vp1 operating voltage range 3.1 5.5 v vp1 uvlo threshold input vo ltage rising 2.9 3 3.1 v vp1 uvlo hysteresis input voltage falling 80 mv standby supply current 130 200 a shutdown supply current reg1 is disabled, v vp1 = 4.2v 0.1 1 a output voltage regulation accuracy v nom1 < 1.3v, i out1 = 10ma -2.4% v nom1 c +1.8% v nom1 1.3v, i out1 = 10ma -1.2% v nom1 +1.8% line regulation v vp1 = max(v nom1 + 1v, 3.2v) to 5.5v 0.15 %/v load regulation i out1 = 10ma to 750ma 0.0017 %/ma current limit 0.85 1.1 a oscillator frequency v out1 20% of v nom1 1.35 1.6 1.85 mhz v out1 = 0v 530 khz pmos on-resistance i sw1 = -100ma 0.28 0.50 ? nmos on-resistance i sw1 = 100ma 0.20 0.35 ? sw1 leakage current v vp1 = 5.5v, v sw1 = 5.5v or 0v 1 a power good threshold 94 %v nom1 minimum on-time 70 ns v
step-down dc/dc converters act8796 rev 2, 16-nov-09 innovative power tm - 13 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi register descriptions address data d7 d6 d5 d4 d3 d2 d1 d0 10h r vrange vset 11h mode 12h r 13h r w/e ok on r r r r r r r r r r r r r r r r r r address name bit access fu nction description 10h vset [5:0] r/w reg1 output voltage selection see table 4 10h vrange [6] r/w reg1 voltage range selection 0 min v out = 1.1v 1 min v out = 1.25v 10h [7] r read only 11h mode [0] r/w mode selection 0 pwm/pfm 1 forced pwm 11h [7:1] r read only 12h [7:0] r read only 13h on [0] r/w reg1 enable 0 reg1 disable 1 reg1 enable 13h ok [1] r reg1 power-ok 0 output is not ok 1 output is ok 13h [2] w/e write-exact 13h [7:3] r read only note: see table 1 for default register settings. table 2: reg1 control register map table 3: reg1 control register bit descriptions r: read-only bits. default values may vary. w/e: write-exact bits. read/write bits which must be written ex actly as specified in table 1
step-down dc/dc converters act8796 rev 2, 16-nov-09 innovative power tm - 14 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi register descriptions cont?d table 4: reg1/vset[ ] output voltage setting reg1/vset[3:0] reg1/vset[5:4] reg1/vrange[ ] = [0] reg1/vrange[ ] = [1] 00 01 10 11 00 01 10 11 0000 n/a n/a 1.455 1.860 1. 250 2.050 2.850 3.650 0001 n/a n/a 1.480 1.890 1. 300 2.100 2.900 3.700 0010 n/a 1.100 1.505 1.915 1. 350 2.150 2.950 3.750 0011 n/a 1.125 1.530 1.940 1. 400 2.200 3.000 3.800 0100 n/a 1.150 1.555 1.965 1. 450 2.250 3.050 3.850 0101 n/a 1.175 1.585 1.990 1. 500 2.300 3.100 3.900 0110 n/a 1.200 1.610 2.015 1. 550 2.350 3.150 3.950 0111 n/a 1.225 1.635 2.040 1. 600 2.400 3.200 4.000 1000 n/a 1.255 1.660 2.065 1. 650 2.450 3.250 4.050 1001 n/a 1.280 1.685 2.090 1. 700 2.500 3.300 4.100 1010 n/a 1.305 1.710 2.115 1. 750 2.550 3.350 4.150 1011 n/a 1.330 1.735 2.140 1. 800 2.600 3.400 4.200 1100 n/a 1.355 1.760 2.165 1. 850 2.650 3.450 4.250 1101 n/a 1.380 1.785 2.190 1. 900 2.700 3.500 4.300 1110 n/a 1.405 1.810 2.200 1. 950 2.750 3.550 4.350 1111 n/a 1.430 1.835 2.245 2. 000 2.800 3.600 4.400 (n/a): not available
step-down dc/dc converters act8796 rev 2, 16-nov-09 innovative power tm - 15 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi c : v nom2 refers to the nominal output voltage level for v out2 as defined by the ordering information section. electrical characteristics (reg2) (v vp2 = 3.6v, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit vp2 operating voltage range 3.1 5.5 v vp2 uvlo threshold input vo ltage rising 2.9 3 3.1 v vp2 uvlo hysteresis input voltage falling 80 mv standby supply current 130 200 a shutdown supply current reg2 disabled, v vp2 = 4.2v 0.1 1 a output voltage regulation accuracy v nom2 < 1.3v, i out2 = 10ma -2.4% v nom2 c +1.8% v nom2 1.3v, i out2 = 10ma -1.2% v nom2 +1.8% line regulation v vp2 = max(v nom2 + 1v, 3.2v) to 5.5v 0.15 %/v load regulation i out2 = 10ma to 750ma 0.0017 %/ma current limit 0.85 1.1 a oscillator frequency v out2 20% of v nom2 1.35 1.6 1.85 mhz v out2 = 0v 530 khz pmos on-resistance i sw2 = -100ma 0.28 0.50 ? nmos on-resistance i sw2 = 100ma 0.20 0.35 ? sw2 leakage current v vp2 = 5.5v, v sw2 = 5.5v or 0v 1 a power good threshold 94 %v nom2 minimum on-time 70 ns v
step-down dc/dc converters act8796 rev 2, 16-nov-09 innovative power tm - 16 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi register descriptions address data d7 d6 d5 d4 d3 d2 d1 d0 20h r vrange vset 21h mode 22h r 23h r w/e ok on r r r r r r r r r r r r r r r r r r address name bit access fu nction description 20h vset [5:0] r/w reg2 output voltage selection see table 7 20h vrange [6] r/w reg2 voltage range selection 0 min v out = 1.1v 1 min v out = 1.25v 20h [7] r read only 21h mode [0] r/w mode selection 0 pwm/pfm 1 forced pwm 21h [7:1] r read only 22h [7:0] r read only 23h on [0] r/w 0 1 23h ok [1] r reg2 power-ok 0 output is not ok 1 output is ok 23h [2] w/e write-exact 23h [7:3] r read only reg2 enable reg2 disable reg2 enable note: see table 1 for default register settings. table 5: reg2 control register map table 6: reg2 control register bit descriptions r: read-only bits. default values may vary. w/e: write-exact bits. read/write bits which must be written ex actly as specified in table 1
step-down dc/dc converters act8796 rev 2, 16-nov-09 innovative power tm - 17 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi register descriptions cont?d table 7: reg2/vset[ ] output voltage setting reg2/vset[3:0] reg2/vset[5:4] reg2/vrange[ ] = [0] reg2/vrange[ ] = [1] 00 01 10 11 00 01 10 11 0000 n/a n/a 1.455 1.860 1. 250 2.050 2.850 3.650 0001 n/a n/a 1.480 1.890 1. 300 2.100 2.900 3.700 0010 n/a 1.100 1.505 1.915 1. 350 2.150 2.950 3.750 0011 n/a 1.125 1.530 1.940 1. 400 2.200 3.000 3.800 0100 n/a 1.150 1.555 1.965 1. 450 2.250 3.050 3.850 0101 n/a 1.175 1.585 1.990 1. 500 2.300 3.100 3.900 0110 n/a 1.200 1.610 2.015 1. 550 2.350 3.150 3.950 0111 n/a 1.225 1.635 2.040 1. 600 2.400 3.200 4.000 1000 n/a 1.255 1.660 2.065 1. 650 2.450 3.250 4.050 1001 n/a 1.280 1.685 2.090 1. 700 2.500 3.300 4.100 1010 n/a 1.305 1.710 2.115 1. 750 2.550 3.350 4.150 1011 n/a 1.330 1.735 2.140 1. 800 2.600 3.400 4.200 1100 n/a 1.355 1.760 2.165 1. 850 2.650 3.450 4.250 1101 n/a 1.380 1.785 2.190 1. 900 2.700 3.500 4.300 1110 n/a 1.405 1.810 2.200 1. 950 2.750 3.550 4.350 1111 n/a 1.430 1.835 2.245 2. 000 2.800 3.600 4.400 (n/a): not available
step-down dc/dc converters act8796 rev 2, 16-nov-09 innovative power tm - 18 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi c : v nom3 refers to the nominal output voltage level for v out3 as defined by the ordering information section. electrical characteristics (reg3) (v vp3 = 3.6v, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit vp3 operating voltage range 3.1 5.5 v vp3 uvlo threshold input vo ltage rising 2.9 3 3.1 v vp3 uvlo hysteresis input voltage falling 80 mv standby supply current 130 200 a shutdown supply current reg3 disabled, v vp3 = 4.2v 0.1 1 a output voltage regulation accuracy v nom3 < 1.3v, i out3 = 10ma -2.4% v nom3 c +1.8% v nom3 1.3v, i out3 = 10ma -1.2% v nom3 +1.8% line regulation v vp3 = max(v nom3 + 1v, 3.2v) to 5.5v 0.15 %/v load regulation i out3 = 10ma to 550ma 0.0017 %/ma current limit 0.65 0.85 a oscillator frequency v out3 20% of v nom3 1.35 1.6 1.85 mhz v out3 = 0v 530 khz pmos on-resistance i sw3 = -100ma 0.35 0.60 ? nmos on-resistance i sw3 = 100ma 0.23 0.40 ? sw3 leakage current v vp3 = 5.5v, v sw3 = 5.5v or 0v 1 a power good threshold 94 %v nom3 minimum on-time 70 ns v
step-down dc/dc converters act8796 rev 2, 16-nov-09 innovative power tm - 19 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi register descriptions address data d7 d6 d5 d4 d3 d2 d1 d0 30h r vrange vset 31h mode 32h r 33h r w/e ok on r r r r r r r r r r r r r r r r r r address name bit access fu nction description 30h vset [5:0] r/w reg3 output voltage selection see table 10 30h vrange [6] r/w reg3 voltage range selection 0 min v out = 1.1v 1 min v out = 1.25v 30h [7] r read only 31h mode [0] r/w mode selection 0 pwm/pfm 1 forced pwm 31h [7:1] r read only 32h [7:0] r read only 33h on [0] r/w reg3 enable 0 reg3 disable 1 reg3 enable 33h ok [1] r reg3 power-ok 0 output is not ok 1 output is ok 33h [2] w/e write-exact 33h [7:3] r read only note: see table 1 for default register settings. table 8: reg3 control register map table 9: reg3 control register bit descriptions r: read-only bits. default values may vary. w/e: write-exact bits. read/write bits which must be written ex actly as specified in table 1
step-down dc/dc converters act8796 rev 2, 16-nov-09 innovative power tm - 20 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi register descriptions cont?d table 10: reg3/vset[ ] output voltage setting reg3/vset[3:0] reg3/vset[5:4] reg3/vrange[ ] = [0] reg3/vrange[ ] = [1] 00 01 10 11 00 01 10 11 0000 n/a n/a 1.455 1.860 1. 250 2.050 2.850 3.650 0001 n/a n/a 1.480 1.890 1. 300 2.100 2.900 3.700 0010 n/a 1.100 1.505 1.915 1. 350 2.150 2.950 3.750 0011 n/a 1.125 1.530 1.940 1. 400 2.200 3.000 3.800 0100 n/a 1.150 1.555 1.965 1. 450 2.250 3.050 3.850 0101 n/a 1.175 1.585 1.990 1. 500 2.300 3.100 3.900 0110 n/a 1.200 1.610 2.015 1. 550 2.350 3.150 3.950 0111 n/a 1.225 1.635 2.040 1. 600 2.400 3.200 4.000 1000 n/a 1.255 1.660 2.065 1. 650 2.450 3.250 4.050 1001 n/a 1.280 1.685 2.090 1. 700 2.500 3.300 4.100 1010 n/a 1.305 1.710 2.115 1. 750 2.550 3.350 4.150 1011 n/a 1.330 1.735 2.140 1. 800 2.600 3.400 4.200 1100 n/a 1.355 1.760 2.165 1. 850 2.650 3.450 4.250 1101 n/a 1.380 1.785 2.190 1. 900 2.700 3.500 4.300 1110 n/a 1.405 1.810 2.200 1. 950 2.750 3.550 4.350 1111 n/a 1.430 1.835 2.245 2. 000 2.800 3.600 4.400 (n/a): not available
step-down dc/dc converters act8796 rev 2, 16-nov-09 innovative power tm - 21 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi r dson (m ? ) vp2 voltage (v) 5.5 0 reg2 mosfet resistance act8796-008 500 400 300 200 100 5.0 4.5 4.0 3.5 3 pmos nmos typical performanc e characteristics act8796-006 out2 regulation voltage out2 voltage accuracy (%) 0.545 temperature (c) -20 0 20 40 60 0.363 0.181 0.000 -0.181 -0.363 85 i out2 = 35ma r dson (m ? ) vp1 voltage (v) 5.5 0 reg1 mosfet resistance 500 400 300 200 100 5.0 4.5 4.0 3.5 3 pmos nmos act8796-005 out1 regulation voltage out1 voltage accuracy (%) 0.545 temperature (c) -20 0 20 40 60 0.363 0.181 0.000 -0.181 -0.363 85 i out1 = 35ma -0.545 -0.545 -40 -40 (act8796qlcia, v vp1 = v vp2 = v vp3 = 3.6v, l = 3.3h, c vp1 = c vp2 = c vp3 = 2.2 f, c out1 = c out2 = c out3 = 10 f, t a = 25c, unless otherwise specified.) act8796-007 reg1 efficiency vs. load current efficiency (%) 95 50 1000 load current (ma) act8796-003 90 80 70 60 1 10 100 v out1 = 1.2v 3.6v 4.2v 85 75 65 55 reg2 efficiency vs. load current efficiency (%) 100 50 1000 load current (ma) act8796-004 90 80 70 60 1 10 100 3.6v v out2 = 2.8v 4.2v
step-down dc/dc converters act8796 rev 2, 16-nov-09 innovative power tm - 22 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi r dson (m ? ) vp3 voltage (v) 5.5 0 reg3 mosfet resistance act8796-011 450 350 250 150 500 400 300 200 100 50 5.0 4.5 4.0 3.5 3 pmos nmos typical performanc e characteristics (act8796qlcia, v vp1 = v vp2 = v vp3 = 3.6v, l = 3.3h, c vp1 = c vp2 = c vp3 = 2.2 f, c out1 = c out2 = c out3 = 10 f, t a = 25c, unless otherwise specified.) reg3 efficiency vs. load current efficiency (%) 1000 output current (ma) act8796-009 90 10 100 3.6v 4.2v v out2 = 1.8v out3 regulation voltage out3 voltage accuracy (%) 0.666 temperature (c) act8796-010 -20 -40 0 20 40 60 0.444 0.222 0.0 -0.222 -0.444 i out1 = 35ma 85 -0.666 85 80 75 70 60 65 55 1 50 95
step-down dc/dc converters act8796 rev 2, 16-nov-09 innovative power tm - 23 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi general description reg1, reg2, and reg3 are fixed-frequency, current-mode, synchronous pwm step down converters that achieve peak efficiencies of up to 97%. reg1 and reg2 are capable of supplying up to 750ma of output current, while reg3 supports up to 550ma. these regulators operate with a fixed frequency of 1.6mhz, minimizing noise in sensitive applications and allowing the use of small external components. each of the step-down dc/dcs are available with a variety of standard and custom output voltages, and each may be software- controlled via the i 2 c interface by systems that require advanced power management functions. 100% duty cycle operation reg1, reg2, and reg3 are each capable of operating at up to 100% duty cycle. during 100% duty-cycle operation, t he high-side power mosfet is held on continuously, providing a direct connection from the input to the output (through the inductor), ensuring the lowest possible dropout voltage in battery powered applications. synchronous rectification reg1, reg2, and reg3 each feature integrated n- channel synchronous rectifiers, maximizing efficiency and minimizing the total solution size and cost by eliminating the nee d for external rectifiers. enabling and disabling reg1, reg2, and reg3 enable/disable functionality is typically implemented as part of a controlled enable/disable scheme utilizing nmstr and other system control features of the act8796. reg1 and reg2 are automatically enabled whenev er either of the following conditions re met: 1) nmstr is driven low, or 2) pwrhld is asserted high. when none of these conditions are true, or if a regulator?s on[ _ ] bit is set to [0], reg1 and reg2 are disabled, and each regulator?s quiescent supply current drops to less than 1a. reg3 is enabled whenever on3 is asserted high, and is disabled whenever on is asserted low or if the reg3/on[ _ ] bit is set to [0]. programming the output voltage by default, reg1, reg2, and reg3 each power up and regulate to their default output voltage. once the system is enabled, each regulator's output voltage may be independently programmed to a different value, typically in order to reduce the power consumption of a mi croprocessor in standby mode. program the output voltages via the i 2 c serial interface by writi ng to the regx/vsetx[ ] and regx/vrange[ ] registers. programmable operating mode by default, reg1, reg2 ,and reg3 each operate in fixed-frequency pwm mode at medium to heavy loads, then transition to a proprietary power-saving mode at light loads in order to save power. in applications where low noise is critical, force fixed- frequency pwm operation across the entire load current range, at the expense of light-load efficiency, by setting the regx/mode[ ] bit to [1]. power-ok reg1, reg2, and reg3 each feature a variety of status bits that can be read by the system microprocessor. if either output voltage is lower than the power-ok threshold, typically 6% below the programmed regulation voltage, regx/ok[ ] will clear to 0. soft-start reg1, reg2, and reg3 each include matched soft-start circuitry. when enabled, the output voltages track the internal 80s soft-start ramp and both power up in a monotonic manner that is independent of loading on either output. this circuitry ensures that each output powers up in a controlled manner, greatly simplifying power sequencing design considerations. compensation reg1, reg2, and reg3 utilize current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over their full operating range. no compensation design is required; simply follow a few simple guidelines described below when choosing external components. functional description
step-down dc/dc converters act8796 rev 2, 16-nov-09 innovative power tm - 24 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi input capacitor selection the input capacitor reduces peak currents and noise induced upon the voltage source. a 2.2f ceramic capacitor for each of reg1, reg2, and reg3 is recommended for most applications. output capacitor selection for most applications, 10f ceramic output capacitors are recommended for reg1, reg2, and reg3. although the these regulators were designed to take advantage of the benefits of ceramic capacitors, namely small size and very-low esr, low-esr tantalum capacitors can provide acceptable results as well. inductor selection reg1, reg2, and reg3 utilize current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over their full operating range. these devices were optimized for operation with 3.3h inductors, although inductor s in the 2.2h to 4.7h range can be used. choose an inductor with a low dc-resistance, and avoid inductor saturation by choosing inductors with dc ratings that exceed the maximum output current of the application by at least 30%. pcb layout considerations high switching frequencies and large peak currents make pc board layout an important part of step- down dc/dc converter design. a good design minimizes excessive emi on the feedback paths and voltage gradients in the ground plane, both of which can result in instability or regulation errors. step-down dc/dcs exhibi t discontinuous input current, so the input capacitors should be placed as close as possible to the ic, and avoiding the use of via if possible. the inductor, input filter capacitor, and output filter capacitor should be connected as close together as possible, with short, direct, and wide traces. the ground nodes for each regulator's power loop should be connected at a single point in a star-ground configuration, and this point should be connected to the backside ground plane with multiple via. the output node for each regulator should be connected to its corresponding outx pin through the shortest possible route, while keeping sufficient distance from switching nodes to prevent noise injection. finally, the exposed pad should be directly connected to the backside ground plane using multiple via to achieve low electrical and thermal resistance. functional description (cont?d)
low-dropout line ar regulators act8796 rev 2, 16-nov-09 innovative power tm - 25 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi electrical characteristics (reg4) (v inl = 3.6v, c out4 = 1f, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit inl operating voltage range 3.1 5.5 v inl uvlo threshold v inl input rising 2.9 3 3.1 v uvlo hysteresis v inl input falling 0.1 v output voltage accuracy v nom4 < 1.3v, i out4 = 10ma -2.4% v nom4 c +1.8% v v nom4 1.3v, i out4 = 10ma -1.2% v nom4 +1.8% line regulation error v inl = max(v out4 + 0.5v, 3.6v) to 5.5v 0 mv load regulation error i out4 = 1ma to 250ma -0.07 mv/ma power supply rejection ratio f = 1khz, i out4 = 250ma, c out4 = 1f 60 db f = 10khz, i out4 = 250ma, c out4 = 1f 50 supply current per output regulator enabled 40 a regulator disabled 0 dropout voltage d i out4 = 120ma, v out4 > 3.1v 100 200 mv output current 250 ma current limit 3 v out4 = 95% of regulation voltage 280 internal soft-start 100 s power good flag high threshold v out4 , hysteresis = -4% 89 % output noise c out4 = 10f, f = 10hz to 100khz 40 v rms stable c out4 range 1 20 f discharge resistor in shutdown ldo disabled, dis4[ ] = [1] 650 ? c : v nom4 refers to the nominal output voltage level for v out4 as defined by the ordering information section. d : dropout voltage is defined as the differential voltage between input and output when the output voltage drops 100mv below the regulation voltage at 1v differential voltage (for 2.8v output voltage or higher) 3 : ldo current limit is defined as the output current at which th e output voltage drops to 95% of the respective regulation volt age. under heavy overload conditions the output current limit folds back by 30% (typ)
low-dropout line ar regulators act8796 rev 2, 16-nov-09 innovative power tm - 26 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi electrical characteristics (reg5) (v inl = 3.6v, c out5 = 1f, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit inl operating voltage range 3.1 5.5 v inl uvlo threshold v inl input rising 2.9 3 3.1 v uvlo hysteresis v inl input falling 0.1 v output voltage accuracy t a = 25c -1.2 v nom5 c +2 % t a = -40c to 85c -2.5 v nom5 +3 line regulation error v inl = max(v out5 + 0.5v, 3.6v) to 5.5v 0 mv load regulation error i out5 = 1ma to 250ma -0.07 mv/ma power supply rejection ratio f = 1khz, i out5 = 250ma, c out5 = 1f 70 db f = 10khz, i out5 = 250ma, c out5 = 1f 60 supply current per output regulator enabled 40 a regulator disabled 0 dropout voltage d i out5 = 120ma, v out5 > 3.1v 100 200 mv output current 250 ma current limit 3 v out5 = 95% of regulation voltage 280 ma internal soft-start 100 s power good flag high threshold v out5 , hysteresis = -4% 89 % output noise c out5 = 10f, f = 10hz to 100khz 40 v rms stable c out5 range 1 20 f discharge resistor in shutdown ldo disabled, dis5[ ] = [1] 650 ? c : v nom5 refers to the nominal output voltage level for v out5 as defined by the ordering information section. d : dropout voltage is defined as the differential voltage between input and output when the output voltage drops 100mv below the regulation voltage at 1v differential voltage (for 2.8v output voltage or higher) 3 : ldo current limit is defined as the output current at which th e output voltage drops to 95% of the respective regulation volt age. under heavy overload conditions the output current limit folds back by 30% (typ)
low-dropout line ar regulators act8796 rev 2, 16-nov-09 innovative power tm - 27 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi electrical characteristics (reg6) (v inl = 3.6v, c out6 = 1f, t a = 25c, unless otherwise specified.) parameter test conditions min typ max unit inl operating voltage range 3.1 5.5 v inl uvlo threshold v inl input rising 2.9 3 3.1 v uvlo hysteresis v inl input falling 0.1 v output voltage accuracy t a = 25c -1.2 v nom6 c +2 % t a = -40c to 85c -2.5 v nom6 +3 line regulation error v inl = max(v out6 + 0.5v, 3.6v) to 5.5v 0 mv load regulation error i out6 = 1ma to 250ma -0.07 mv/ma power supply rejection ratio f = 1khz, i out6 = 250ma, c out6 = 1f 70 db f = 10khz, i out6 = 250ma, c out6 = 1f 60 supply current per output regulator enabled 40 a regulator disabled 0 dropout voltage d i out6 = 120ma, v out6 > 3.1v 100 200 mv output current 250 ma current limit 3 v out6 = 95% of regulation voltage 280 ma internal soft-start 100 s power good flag high threshold v out6 , hysteresis = -4% 89 % output noise c out6 = 10f, f = 10hz to 100khz 40 v rms stable c out6 range 1 20 f discharge resistor in shutdown ldo disabled, dis6[ ] = [1] 650 ? c : v nom6 refers to the nominal output voltage level for v out6 as defined by the ordering information section. d : dropout voltage is defined as the differential voltage between input and output when the output voltage drops 100mv below the regulation voltage at 1v differential voltage (for 2.8v output voltage or higher) 3 : ldo current limit is defined as the output current at which th e output voltage drops to 95% of the respective regulation volt age. under heavy overload conditions the output current limit folds back by 30% (typ)
low-dropout line ar regulators act8796 rev 2, 16-nov-09 innovative power tm - 28 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi register descriptions note: see table 1 for default register settings. table 11: control register map address data d7 d6 d5 d4 d3 d2 d1 d0 03h r vrange vset4 40h r r w/e r r r r r 41h r r on5 vset5 42h r r on6 43h ok6 ok5 ok4 dis6 dis5 dis4 w/e r vset6 address name bit access fu nction description 03h vset4 [5:0] r/w reg4 output voltage selection see table 14 03h vrange [6] r/w reg4 output voltage selection 0 min vout = 0.645v 1 min vout = 1.25v 03h [7] r read only 40h [4:0] r read only 40h [7:6] r read only 41h vset5 [4:0] r/w reg5 output voltage selection see table 13 41h on5 [5] r/w reg5 enable 0 reg5 disable 1 reg5 enable 41h [7:6] r read only 42h vset6 [4:0] r/w reg6 output voltage selection see table 13 42h on6 [5] r/w reg6 enable 0 reg6 disable 1 reg6 enable 42h [7:6] r read only 43h [0] r read only 43h [1] w/e write-exact 40h [5] w/e write-exact table 12: reg56 control register bit descriptions r: read-only bits. default values may vary. w/e: write-exact bits. read/write bits which must be written exac tly as specified in table 1.
low-dropout line ar regulators act8796 rev 2, 16-nov-09 innovative power tm - 29 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi register descriptions cont?d table 13: reg56/vsetx[ ] output voltage setting reg56cfg/vsetx[2:0] reg56cfg/vsetx[4:3] 00 01 10 11 000 1.4 2.15 2.55 3.0 001 1.5 2.20 2.60 3.1 010 1.6 2.25 2.65 3.2 011 1.7 2.30 2.70 3.3 100 1.8 2.35 2.75 3.4 101 1.9 2.40 2.80 3.5 110 2.0 2.45 2.85 3.6 111 2.1 2.50 2.90 3.7 address name bit access fu nction description 43h dis4 [2] r/w reg4 discharge enable 0 discharge disable 1 discharge enable 43h dis5 [3] r/w 0 discharge disable 1 discharge enable 43h dis6 [4] r/w reg6 discharge enable 0 discharge disable 1 discharge enable 43h ok4 [5] r reg4 power-ok 0 output is not ok 1 output is ok 43h ok5 [6] r reg5 power-ok 0 output is not ok 1 output is ok 43h ok6 [7] r reg6 power-ok 0 output is not ok 1 output is ok reg5 discharge enable table 12: control register bit descriptions (cont?d)
low-dropout line ar regulators act8796 rev 2, 16-nov-09 innovative power tm - 30 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi register descriptions cont?d table 14: reg4/vrange[ ] output voltage setting reg4/vset[3:0] reg4/vset[5:4] reg4/vrange[ ] = [0] reg4/vrange[ ] = [1] 00 01 10 11 00 01 10 11 0000 0.645 1.050 1.455 1.860 1.250 2.050 2.850 3.650 0001 0.670 1.075 1.480 1.890 1.300 2.100 2.900 3.700 0010 0.695 1.100 1.505 1.915 1.350 2.150 2.950 n/a 0011 0.720 1.125 1.530 1.940 1.400 2.200 3.000 n/a 0100 0.745 1.150 1.555 1.965 1.450 2.250 3.050 n/a 0101 0.770 1.175 1.585 1.990 1.500 2.300 3.100 n/a 0110 0.795 1.200 1.610 2.015 1.550 2.350 3.150 n/a 0111 0.820 1.225 1.635 2.040 1.600 2.400 3.200 n/a 1000 0.845 1.255 1.660 2.065 1.650 2.450 3.250 n/a 1001 0.870 1.280 1.685 2.090 1.700 2.500 3.300 n/a 1010 0.895 1.305 1.710 2.115 1.750 2.550 3.350 n/a 1011 0.920 1.330 1.735 2.140 1.800 2.600 3.400 n/a 1100 0.950 1.355 1.760 2.165 1.850 2.650 3.450 n/a 1101 0.975 1.380 1.785 2.190 1.900 2.700 3.500 n/a 1110 1.000 1.405 1.810 2.200 1.950 2.750 3.550 n/a 1111 1.025 1.430 1.835 2.245 2.000 2.800 3.600 n/a (n/a): not available
low-dropout line ar regulators act8796 rev 2, 16-nov-09 innovative power tm - 31 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi typical performanc e characteristics (act8796qlcia, v vin = 5v, t a = 25c, unless otherwise specified.) load regulation output voltage (v) load current (ma) 0.5 act8796-013 0 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 dropout voltage (mv) output current (ma) 200 dropout voltage vs. output current act8796-014 160 50 0 150 100 200 output voltage deviation vs. temperature output voltage deviation (%) temperature (c) -40 85 act8796-015 10 35 60 ldo output voltage noise ch1 ch1: v outx , 200v/div (ac coupled) time: 200ms/div c ref = 10nf 25 50 75 100 125 150 175 200 225 250 140 180 120 100 80 60 40 20 0 250 v in = 3.1v v in = 3.3v v in = 3.6v 0.5 -0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 act8796-017 act8796-016 -0.5 -15 i load = 0ma region of stable c out esr vs. output current 0.1 1 0.01 250 200 150 100 50 0 output current (ma) esr ( ? ) stable esr -0.4
low-dropout line ar regulators act8796 rev 2, 16-nov-09 innovative power tm - 32 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi general description reg4, reg5, and reg6 are low-noise, low- dropout linear regulators (ldos) that are optimized for low noise and high-psrr operation, achieving more than 60db psrr at frequencies up to 10khz. ldo output voltage programming all ldos feature independently-programmable output voltages that are set via the i 2 c serial interface, increasing the act8796?s flexibility while reducing total solution size and cost. set the output voltage by writing to the reg456cfg/vsetx[ ] registers. output current capability reg4, reg5, and reg6 each supply an output current of 250ma. excellent performance is achieved over this load current range. output current limit in order to ensure safe operation under over-load conditions, each ldo features current-limit circuitry with current fold-back. the current-limit circuitry limits the current that can be drawn from the output, providing protection in over-load conditions. for additional protection unde r extreme over current conditions, current-fold-back protection reduces the current-limit by approximately 30% under extreme overload conditions. enabling and disabling the ldos reg4 is enabled whenever either of the following conditions are met: 1) nmstr is driven low, or 2) pwrhld is asserted high. furthermore, once these conditions are met reg5 and reg6 maybe independently enabled or disabled via the i 2 c serial interface by writing the appropriate reg56/onx[ _ ] bit. power-ok each of the ldos features power-ok status bit that can be read by the system microprocessor via the i 2 c interface. if an output voltage is lower than the power-ok threshold, typically 6% below the programmed regulation voltage, the corresponding reg456cfg/okx[ ] will clear to 0. reference bypass pin the act8796 contains a reference bypass pin which filters noise from the reference, providing a low noise voltage reference to the ldos. bypass ref to g with a 0.01f ceramic capacitor. optional ldo output discharge each of the act8796?s ldos features an optional, independent output voltage discharge feature. when this feature is enabled, the ldo output is discharged to ground through a 1k ? resistance when the ldo is shutdown. this feature may be enabled or disabled via the i 2 c interface by writing to the reg456cfg/disx[ ] bits. output capacitor selection reg4, reg5, and reg6 each require only a small ceramic capacitor for stability. for best performance, each output capacitor should be connected directly between the outx and g pins as possible, with a short and direct connection. to ensure best performance fo r the device, the output capacitor should have a minimum capacitance of 1f, and esr value between 10m ? and 200m ? . high quality ceramic capacitors such as x7r and x5r dielectric types are strongly recommended. pcb layout considerations pcb layout considerations the act8796?s ldos provide good dc, ac, and noise performance over a wide range of operating conditions, and are relatively insensitive to layout considerations. when designing a pcb, however, careful layout is necessary to prevent other circuitry from degrading ldo performance. a good design places input and output capacitors as close to the ldo inputs and output as possible, and utilizes a star-ground configuration for all regulators to prevent noise-coupling through ground. output traces should be routed to avoid close proximity to noisy nodes, particularly the sw nodes of the dc/dcs. refbp is a filtered reference noise, and internally has a direct connection to the linear regulator controller. any noise injected onto refbp will directly affect the outputs of the linear regulators, and therefore special care should be taken to ensure that no noise is injected to the outputs via refbp. as with the ld o output capacitors, the functional description
low-dropout line ar regulators act8796 rev 2, 16-nov-09 innovative power tm - 33 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi refbp bypass capacitor should be placed as close to the ic as possible, with short, direct connections to the star-ground. avoid the use of via whenever possible. noisy nodes, such as from the dc/dcs, should be routed as far away from refbp as possible. functional description (cont?d)
act8796 rev 2, 16-nov-09 package outline and dimensions innovative power tm - 34 - www.active-semi.com copyright ? 2009 active-semi, inc. activepmu tm is a trademark of active-semi. i 2 c tm is a trademark of philips electronics. active- semi package outline tqfn44-24 package outline and dimensions a d d/2 e e/2 a3 a1 d2 e2 e b l r k pin #1 index area d/2 x e/2 pin #1 index area d/2 x e/2 symbol dimension in millimeters dimension in inches min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.200 ref 0.008 ref b 0.180 0.300 0.007 0.012 d 3.850 0.152 e 3.850 0.152 d2 2.500 2.800 0.098 0.110 e2 2.500 2.800 0.098 0.110 e 0.500 bsc 0.020 bsc l 0.350 0.450 0.014 0.018 r 0.200 typ 0.008 typ 4.150 4.150 0.163 0.163 k 0.200 0.008 --- --- active-semi, inc. reserves the right to modify the circuitry or specifications without notice. user s should evaluate each product to make sure that it is suitable for their applicat ions. active-semi products are not intended or authorized for use as critical components in life-support dev ices or systems. active-semi, inc. does not assume any liability arising out of the use of any product or circuit described in this datasheet, nor does it convey any patent license. active-semi and its logo are trademarks of active-semi, inc. for more information on this and other products, contact sales@active-semi.com or visit http://www.active-semi.com. for other inquiries, please send to: 2728 orchard parkway, san jose, ca 95134-2012, usa

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